Friday, April 19, 2024

HP Leaps Toward Next-Generation Memory

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Researchers at Hewlett-Packard have announced three breakthroughs in the field of molecular electronics, which combine to give a glimpse of the future of memory.

HP scientist R. Stanley Williams, an HP Fellow and director of Quantum Science Research at HP Labs and his group have:

  • created the highest density electronically addressable memory reported to date.
  • combined, for the first time, both memory and logic using rewritable, nonvolatile molecular-switch devices; and
  • fabricated the circuits using a process called nano-imprint lithography.

Williams introduced his group’s achievements in Stockholm, Sweden, at a symposium celebrating the 175th anniversary of the Royal Institute of Technology of Sweden.

HP has a laboratory prototype for a 64-bit memory that uses molecular switches as active devices. It features a bit density more than 10 times greater than today’s silicon memory chips, and it fits inside a square micron.

To make the chips, the researchers made a master mold of eight parallel lines, each only 40 nanometers wide. They then pressed the mold into a polymer layer on a silicon wafer to make eight parallel “east-west” trenches, which were filled with platinum metal to form wires. A single layer of electronically switchable molecules was then deposited on the surface. The process was repeated after rotating the mold 90 degrees to make another eight wires, running “north-south,” on top of the molecular layer.

There were 64 points where the wires intersected, and roughly 1,000 molecules sandwiched between the wires, each of which became a bit of memory. The bits are written by applying a voltage pulse to set the molecules’ electrical resistance and read by measuring their resistance at a lower voltage.

The researchers also put logic in the same circuit by configuring molecular-switch junctions to make a demultiplexer — an essential logic circuit that uses a small number of wires to address memory.

Williams said he would like to see commercialization of such a memory in five to 10 years. “Our most optimistic hope hope for this type of technology is five years,” he said.

The first products resulting from the work would likely be aimed at niche memory markets, such as Flash memory and other areas where a need for inexpensive, nonvolatile memory exists.

To demonstrate just how nonvolatile the memory is, Williams said the stage of a switch was set, and it was basically put on a shelf to see how the charge would hold. Four months later, it was still set. “That’s the basis for a very high-quality, nonvolatile switch,” Williams said.

As for capacity, Williams believes the technology, which has been demonstrated at 6.4 gigabits per square centimeter, is scalable to 100 gigabits per square centimeter.

Such a memory is expected to have a cost advantage over Flash memory when it hits the market because of the manufacturing process. The nano-imprint technology that was used is a technique that Williams compared to the early printing press. It allows an entire wafer of circuits to be stamped from of a master. In this case, the master is made using electron beam lithography, a time-consuming process that isn’t considered practical for manufacturing. Once the master is made, however, it can be used to make, for example, 1 million chips, which then spreads the cost of the electron beam lithography over the 1 million chips.

Combining the nano-imprint lithography, which would serve as an alternative to increasingly expensive photolithography, with the simplicity of the cross-bar architecture will result in a low cost per bit.

“We view this as a highly manufacturable and scalable process,” Williams said.

While it all sounds good, the trick will be getting the rather conservative world of electronics manufacturing to accept what Williams and his team have done. “In a sense we need to change a large part of the paradigm of electronics manufacturing,” Williams said.

The best hope is that the industry finds what Williams and his team accomplished compelling enough to license the technology from HP. In order for the technology to succeed, Williams said there will need to be more than one supplier so the market is open to competition.

As the memory continues to develop, there is also the possibility that Williams and company have found a technique that will allow memory to get to a theoretical limit — where each individual molecule is used as a bit. Williams said at such a scale the wires would need to be shrunk to 1 nanometer in size, which would require about seven years of work from where they are now. The density of such a memory, however, would be more than 1 terabit per square centimeter.

“Getting down to a single molecule is certainly our aspiration,” Williams said. “But it’s not clear what the physics of the switching process is.”

In this series of pictures, taken with optical and scanning electron microscopes, each image is magnified approximately 10 times more than the previous one. A) The wafer on which 625 memories and their test structures were simultaneously imprinted. B) An array of memories with their test connections. C) A single test structure with the memory, which is still invisible at this magnification, in the center. D) Nanowires leading from the test pins to the memory at the intersection of the lines. E) The crossed-wire structure of the memory. F) A close-up of a single 64-bit memory. A bit can be stored at each of the intersections of the eight vertical and eight horizontal wires. Photos courtesy of Hewlett-Packard.

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