Road Trip For Intel's Chips

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When Intel began a series of cost-cutting measures late last year, the Spring Intel Developer Forum (IDF) was going to be one of the casualties. Normally, IDF is a twice-yearly ritual, held in San Francisco’s Moscone Center, but Intel was ready to make it a once-a-year event.

Instead, Intel (Quote) took the event on the road to what it considered a happening market, China. “The main reason for a Chinese IDF was they needed to have a presence there, so it made sense for them to go forward there,” said semiconductor analyst Dean McCarron of Mercury Research.

With no IDF in the U.S., the company tipped its hand on what McCarron felt would have surely been the big news, the Nehalem processor family. Intel released details on Nehalem last month.

That’s not to say there is no news out of China. In his keynote speech, Pat Gelsinger, senior vice president and general manager of the Digital Enterprise Group announced “Tolapai,” Intel’s first foray into “system-on-chip” (SoC) products. Tolapai products will ship in 2008 and should reduce the chip footprint size by up to 45 percent and power consumption by approximately 20 percent compared to standard chip design.

Gelsinger also provided some benchmarks for Penryn-based desktop processors. Intel said to expect a 15 percent increase in imaging-related application performance; a 25 percent increase for 3-D rendering; more than 40 percent for gaming and more than 40 percent faster video encoding with the new SSE4 instructions.

For high-performance computing (HPC) and workstation systems, expect performance gains up to an estimated 45 percent for bandwidth intensive applications and a 25 percent increase for servers using Java.

Sean Maloney, executive vice president and chief sales and marketing officer for Intel briefed the press via conference call. Intel is moving into volume production of multiple new processors, all on 45nm technology, thanks to the Hi-k and metal gate breakthrough it announced in January.

“The Hi-k and metal gate breakthrough was big,” he said on the call. “The magic of integration can continue out into the future in terms of smaller, faster, more powerful chips and better thermal characteristics.”

Intel’s product roadmap reads like a regular map, since all of its codenames come from Oregon and Northern California landmarks. Coming later this year will be the Harpertown and Yorkfield Xeon processors, both 45nm, featuring eight cores and up to 16MB of cache.

Intel’s Chief Technology Officer Justin Rattner had a demo of his own where he showed the 80 core terascale processor running at over two teraflops, not one teraflop as previously claimed. He also outlined an initiative by Intel to achieve a ten-fold power reduction by 2010.

Intel has a new brand of Xeon processors, the 7300 series of high-end quad and dual multi-processor servers codenamed “Caneland.” These will be designed for blade systems and draw just 80 or 50 watts of power. They represent the final family of processors to move to the Core microarchitecture.

Also, a Sun executive will be on-hand in China to demonstrate the Solaris operating system running on an Xeon 5100-based system using Intel Dynamic Power technology.

Separate from IDF, Intel made some announcements at the Storage Networking World conference in San Diego as well. The company announced what it claims is the industry’s first 2U, 12 drive, integrated quad-core storage server, the Intel Storage Server SSR212MC2.

This Xeon 5300-based rack mount server is aimed at the small- and medium-sized business (SMB) (define) market and can be configured to serve as Network-Attached Storage (NAS), Storage Area Network (SAN) and application servers.

Intel said it has support from Microsoft, FalconStor, Open-E, Open SuSE, RedHat and Wasabi Systems for the SSR212MC2. It will be available in May and cost $2,800 with no RAID controller or $3,600 with the Intel SRCSAS144e RAID Controller.

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