An MIT-inspired startup will introduce a new multi-core chip today at the annual Hot Chips conference at Stanford University. The TILE64 boasts a “clean sheet” design, unencumbered by any legacy compatibility concerns, that Tilera says will provide a huge leap in multithreaded performance.
Tilera was founded in 2004 to bring to market the multi-core processor designs of MIT researcher Anant Agarwal. Agarwal created what he called a “mesh” multi-core architecture, where the cores are all interconnected rather than going through a frontside bus, as Intel’s multi-core chips do.
Agarwal first created this multi-core architecture in 1996, long before Intel and AMD were anywhere close to doing it. The project received funding from the Defense Advanced Research Project Agency (DARPA) and the National Science Foundation, the agency that managed the Internet for decades.
Tilera holds 40-plus patents for its multi-core design. TIL64 will be the first in a series of processors built around massively multi-core chips. The TILE64 processor contains 64 full-featured, programmable cores that Tilera claims can perform 500 billion operations per second and delivers ten times the performance and thirty times the performance-per-watt of the Intel dual-core Xeon.
Agarwal said the company can make these performance leaps because it doesn’t use any legacy technologies or designs.
“The real problem with scale is existing multi-core architectures use a bus. In that architecture, the bus is a central switch and all the cores are connected to the single central switch. A packet has to go through it no matter what, which is fine for one, two or four cores, but it does not scale,” he told internetnews.com.
Tilera uses a mesh architecture, where the cores are laid out in a checkerboard-like grid, all connected through high-speed interconnects. “In architectures of this sort, you can keep growing and you won’t have any serious congestion,” said Agarwal.
Intel has promised to dispense with the frontside bus with the Nehalem architecture, due late next year. AMD does not have a frontside bus in the Opteron, but it’s also using four cores at the most, while Tilera is at 64.
The TILE family can scale up to even more, or down to a two-core design for the smallest of designs, such as a cell phone. Its power consumption is a few hundred milliwatts per core, Agarwal said. Its clock speed will range from 600MHz to 1GHz.
But there’s a lot more on the chip than just cores. It has a pair of 10 gigabit Ethernet ports directly on the chip for high speed networking, as well as on-board I/O and peripheral controllers. Its integrated memory controllers allow for up to 200 gigabits of memory bandwidth within the chip.
That’s what made the TILE64 chip so appealing to Top Layer, developer of network security and intrusion detection appliance. The company had built its own processors but now plans to switch to Tilera’s chips, according to Chief Strategy Officer Mike Paquette.
“Our software is a multi-core design, and we were able to map out functionality almost 1 for 1 for each process to a core in a Tilera chip,” he said. “The performance we expect in our estimates exceeds what we could have gotten from any silicon providers.”
Top Layer decided to license processors for future products rather than the expense of building any more, and no other processors had the scalability. “Because the movement of data is so much of what we do, we needed a multi-core chip that was optimized for what we were doing rather than something optimized for general purpose computing Tilera has capabilities for network capabilities that are far ahead of what you can get from [x86] processors,” said Paquette.