Lessons Learned From AMD's Barcelona Mess

Shanghai will see more testing, improved internal communication and early exposure to OEM partners in hopes of avoiding another disastrous launch.

AMD roadmap

SAN FRANCISCO -- AMD's Barcelona launch was bumpier than a 737 departing Chicago into a storm off the Great Lakes. Plagued by delay after delay, then by a bug in the processor after it was supposed to ship, Barcelona was a lesson in how not to launch a new product.

AMD (NYSE: AMD) insists it learned that lesson.

The company discussed the problem with reporters yesterday, and the steps it's taking to ensurethat Shanghai, its next server processor, will not be another Barcelona, the codename for its Quad-Core Opteron.

"Coming up with design goals is easy," Patrick Patla, general manager of the server and workstation division, told the group. "But the [Barcelona] project had to have high confidence in the schedule. It had partners who felt burned by the execution in Barcelona and had to see that Shanghai was not going to be a Barcelona redux."

To a large degree, that's made easier by the fact that Shanghai's development is a smaller, iterative step. As the first quad-core, Barcelona, meanwhile, required almost a wholly new design -- requiring 80 percent of its design and the process to build it having to be created from scratch.

Still, Shanghai faces at least one major hurdle: going from a 65-nanometer design to a 45nm process.

"Less change made it easier, but don't underestimate going to a new process -- you don't want to do that," Patla later told InternetNews.com. "We knew it was doing good things but still wanted to make sure we matched the design process to the layout."

Much more careful this time

To prevent another Barcelona-like meltdown, all of the design teams involved in the chip's production had a meeting in January, during which they made sure everyone understood the changes in Shanghai and what had to be done.

AMD also extended and expanded Shanghai's testing process to make sure all potential scenarios were covered. It didn't find the errata bug in Barcelona until the product was ready to ship, because only then had it been tested in a virtualized environment -- something AMD forgot to do earlier. This time, they made sure to test Shanghai eight ways from Sunday -- in every potential usage model, particularly virtualization.

AMD also brought OEM partners into the design process earlier, so they could see what was on the plate. As a result, AMD spent an extra month in simulation testing before the first "tape out," when it creates the first batch of sample processors for testing. Up to that point, the chip had been run as a software simulation on computers.

The company delayed the first tape out to do more simulation testing, to see in particular how the processor would behave in a virtualized environment, since that's where the errata bug appeared the last time.

The shift to a smaller, more efficient 45-nanometer design is critical for AMD. Intel made the move to high-k metal gate technology to reduce power leakage, but AMD said it thinks the silicon on insulator (SOI) technology at the core of its designs will allow it to go to 45nm without needing a wholly new approach.

In addition to potentially being more efficient, there are other benefits to Shanghai's new design. The immersion lithography used in the new chip gives it what Patla called "well-behaved transistors," offering 20 percent better performance over Barcelona at the same clock speed. That will lead to a 35 percent performance improvement overall, since Shanghai will have higher clock speeds than Barcelona.

Those performance numbers depend on workload, he added. One of the biggest differences between Shanghai and Barcelona is the L3 cache. Barcelona has 2MB of L3 cache shared among its four cores, while Shanghai will have 6MB of L3 cache. The most likely applications to see snappier performance due to the larger cache are databases and Java machines, as a database can hold more data in its cache and Java applets are small enough to reside entirely in-cache, Patla said.

AMD said it's learned its lesson after Barcelona's painful development, but chip analyst Nathan Brookwood of Insight64 wonders if the company has become too cautious in the process.

"They may have gotten gun-shy because Barcelona was very painful and they cannot have another episode like that without really causing their customers to question their predictability," he told InternetNews.com.

For example, he noted that AMD's future product plans for the next two years are very conservative.

"Their roadmap is extremely cautious over the next few years ... There is nothing on the roadmap that is as complicated or introduces as many new things at once as Barcelona did," he said. "So if the lesson from Barcelona is be careful and don't bite off more than you can chew, yes, they learned that lesson."

Accelerated launch plans

Still, AMD is optimistic about Shanghai -- and has even moved up its launch schedule based on early successes.

"Everything from a design-goal perspective is behaving as we wanted it to," Patla said.

As a result, the company is now saying it will launch Shanghai in fourth quarter, with OEM platforms and the processors themselves coming to market by then. The original guidance had been to merely begin chip production during the quarter.

The processors are socket-compatible with existing Barcelona designs, so all existing server administrators would need to do, besides a BIOS (define) upgrade, is to pop out the old processor and replace it with the new one.

This article was first published on InternetNews.com.

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