The increased density would greatly reduce the amount of energy needed to power the chips.
The company said the new chips could be built using the same sized transistors used in current FPGA design, so they could be built in current fabrication plants with minor modification.
"As conventional chip electronics continue to shrink, Moore's Law (define) is on a collision course with the laws of physics," said Stan Williams, an HP senior fellow and director of Quantum Science Research at HP Labs. "Excessive heating and defective device operation arise at the nanoscale.
The research was led by Williams, along with fellow researcher Greg Snider who is a senior architect with Quantum Science Research for HP Labs.
The technology calls for a nanoscale crossbar switch structure to be layered on top of conventional CMOS (define) using an architecture HP Labs researchers have named "field programmable nanowire interconnect (FPNI)" -- a variation of FPGA technology.
In the FPNI approach, all logic operations are performed in the CMOS, whereas most of the signal routing in the circuit is handled by a crossbar that sits above the transistor layer.
Since conventional FPGAs use 80 percent to 90 percent of their CMOS for signal routing, the FPNI circuit is much more efficient; the density of transistors actually used for performing logic is much higher, and the amount of electrical power required for signal routing is decreased.
But none of this is coming soon. The researchers presented what they said is a "conservative" chip model using 15-nanometer-wide crossbar wires combined with 45-nm half-pitch CMOS, which they said they believe could be technologically viable by 2010. It could well be worth the wait.
Snider and Williams said if implemented, the FPNI chips would be equivalent to leaping ahead three generations on the international technology roadmap for silicon without having to shrink the transistors.
"The expense of fabricating chips is increasing dramatically with the demands of increasing manufacturing tolerances," said Snider. "We believe this approach could increase the usable device density of FPGAs by a factor of eight, using tolerances that are no greater than those required of today's devices."