In October or November, Intel is expected to ship its next-generation "Prescott" desktop CPU -- not as radical a change as AMD's Athlon 64, but an evolution of the Pentium 4 to a smaller, faster, more powerful design. Expected enhancements include microarchitecture and cache changes, not to mention higher clock speeds -- all made possible by the biggest advance of all, the move from 0.13-micron to 90-nanometer (0.09-micron) process architecture.
Prescott's anticipated 1MB of Level 2 cache is double that of current Pentium 4 processors. As with the 0.13-micron Athlon 64, squeezing all that SRAM onto the die requires a lot of transistors, which might negatively affect chip yields, but the higher density of 90-nanometer design makes it easier for Intel to add more cache and still get a cost-effective number of chips per wafer. Prescott also doubles the Pentium 4's Level 1 cache from 8K to 16K, and even though the numbers are small, the performance impact could be significant.
It will all add up to nearly 100 million transistors per chip, obliging Intel to introduce various internal improvements to boost efficiencies and reduce core voltages -- to a rumored 1.1 to 1.25 volts, versus today's Pentium 4 parts' 1.5-plus.
These are important considerations, especially if Prescott is to hit the clock speeds projected for it -- while the CPU may debut at little more than the current Pentium 4's 3.2GHz, analysts expect 4GHz if not 5GHz in the relatively near future. Considering that the original, 0.18-micron-process P4 core reached 2.0GHz, double that would seem to be an easy target for the 90-nanometer Prescott, but only time will tell, as die size is just one facet of the quest for clock speed. The front-side bus speed is expected to stay at 800MHz, though as Intel has shown with the P4, this may be only temporary.
Hyper-Threading Technology is a top-priority initiative for Intel, and Prescott will be the first processor line to include this mock-multiprocessing, better-multitasking feature from top to bottom. Intel has also alluded to new x86 instructions and improvements in Hyper-Threading efficiencies, which -- if the chip giant gets its wish and software developers optimize all their wares for the technology -- could turn Hyper-Threading from today's "nice to have" status or 5- to 15-percent performance boost into a formidable weapon against AMD.
There are several open questions regarding Intel's Prescott, related mostly to its release date and projected name. Currently, as mentioned, October is the optimistic and November the cautious prediction, but this could be subject to change, especially given the shift to a new 90-nanometer process. Nvidia learned this lesson with its late-to-market GeForce FX, and introducing unproven technology is always risky, even for Intel.
The brand-name betting is turning into an Internet side show, with most predicting that tradition -- and the several iterations that have already put different Pentium 4 models' comparative clock speeds out of sync with real-world performance results -- will dictate a fresh start with the label Pentium 5. On the other hand, the name Sexium definitely has its fan base.
In short, Intel and AMD are gearing up for another round in their head-to-head battle for desktop CPU supremacy, and each has adjusted its strategy or tuned its technology to adapt to the competition. AMD can't compete with the insanely high clock speeds that Intel can reach, so the Athlon 64 design stresses architectural efficiencies and 64-bit compatibility. Its integrated memory controller is one of AMD's key advances, and the prospect of a dual-channel successor has likely caught the attention of Intel's engineering department.
Likewise, the Intel Prescott and accompanying chipsets will need an answer on Day 1 for the faster memory accesses of the Athlon 64's on-die memory controller, though doubling the L2 cache to 1MB is an obviously good gambit. Look for this type of punch and counterpunch to continue into 2004 -- or until Microsoft and its level of AMD64 support get the last word in the eventual success of either CPU.