Intel Lays Out Itanium Roadmap

'Out of a Chevette and into a Corvette.'
Intel Thursday extended its roadmap for the Itanium processor, affirming its commitment to the EPIC technology chip through several revisions over the next few years. The company is looking to increase its core and thread count, as well as incorporate some technologies from other products.

Diane Bryant, vice president of the digital enterprise group at Intel (Quote)  said on a conference call that the Itanium product line has two separate teams working on different versions. One team consists of developers involved in HP's (Quote) PA-RISC (define) chip, while another team in New England is made up of former developers of the DEC Alpha processor.

Compaq purchased DEC in 1998 and sold off the Alpha line to Intel in 2001 shortly before HP bought out Compaq. HP ended its Itanium development efforts in 2004 and Intel acquired that staff.

Itanium has been slowly ramping up, Bryant noted, and now accounts for 63 percent of the RISC market. Itanium systems revenue in 2006 were $3.4 billion, a 40 percent growth over 2005 revenues.

Intel released the dual-core Itanium 2, code-named Montecito, in July 2006. The Itanium ecosystem has grown to 12,000 applications, a 100 percent growth from 2005 to 2006, and most of those apps run on either Windows or Linux.

Intel is on track to release Montvale, the follow-up processor to the Montecito processors in the second half of 2007. Not a whole lot was discussed, considering the chip is so close to release. Bryant only mentioned improvements in reliability as a notable feature.

She did talk at length about Tukwila, due in late 2008. It will be twice as fast as the current processors, feature four cores, hyper-threading technology supporting up to eight threads per core, large on-die caches, integrated memory controllers that do away with the front-side bus (like Nehalem will do on the desktop) and new memory error detection.

This feature is called Double Device Data Correction (DDDC), a RAS (define) capability that allows a memory DIMM to continue operation even if it suffers two sequential DRAM device hard-errors, i.e. chip failures. Today, some systems can keep running if one chip on a DRAM stick fails, but if two chips fail, the whole DIMM fails and can crash a system.

After that will come Poulson, which will be the first new Itanium architecture since the Itanium 2 was introduced in 2002. Poulson will emphasize scalability, performance, reliability and flexibility with more cores, more threads and more instructions per cycle. Poulson will be based on 32nm designs, skipping 45nm entirely.

Beyond that is Kittson, which will increase parallelism and add even more cores and threads. She did not say when Intel hopes to release Poulson and Kittson.

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